Panel Configuration Generator
LCD Display Configuration
Bus Type
No LCD
SPI
I2C
I8080 Parallel
RGB
MIPI DSI
Include Code
Extra Reset Procedure
Vendor Specific Configuration
Transfer Buffer Translation
Panel Initialization
Horizontal Resolution
Vertical Resolution
Color Space
Swap Color Bytes
Invert Color (Common for IPS)
Color Bit Depth
X Offset (Gap)
Y Offset (Gap)
X Flush Alignment
Y Flush Alignment
Swap X and Y
Mirror X
Mirror Y
Reset Pin
Reset On Level
Backlight Pin
Backlight On Level
Transfer Divisor
Transfer Buffer Size
Transfer Buffer Has Palette
Transfer Buffer Palette Size
Transfer Buffer in PSRAM
Use Fullscreen Transfers
Use Synchronous Transfers
SPI Configuration
SPI Host
Clock (MHz)
Command Bits
Param Bits
Pin Configuration
MOSI/Data 0 Pin
MISO/Data 1 Pin
QuadWP/Data 2 Pin
QuadHD/Data 3 Pin
Data 4 Pin
Data 5 Pin
Data 6 Pin
Data 7 Pin
Clock Pin
Chip Select Pin
Data/Command Pin
I2C Configuration
I2C Host
Clock (KHz)
I2C Address
Use Internal Pullups
Command Bits
Param Bits
DC Bit Offset
Control Phase Bytes
Disable Control Phase
Pin Configuration
SDA Pin
SCL Pin
I8080 Configuration
Clock (MHz)
Command Bits
Param Bits
CS On Level
DC/RS On Level
Reverse Color Bits
Pin Configuration
Data 0 Pin
Data 1 Pin
Data 2 Pin
Data 3 Pin
Data 4 Pin
Data 5 Pin
Data 6 Pin
Data 7 Pin
Data 8 Pin
Data 9 Pin
Data 10 Pin
Data 11 Pin
Data 12 Pin
Data 13 Pin
Data 14 Pin
Data 15 Pin
Chip Select Pin
Data/Command/RS Pin
Write Pin
Read Pin
RGB Configuration
Clock (MHz)
Little Endian Data
Clock On Level
Clock Active Negative
Framebuffer Count
Data Enable On Level
VSYNC On Level
Display Command On Level
Timing Parameters
HSYNC Pulse Width
HSYNC Back Porch
HSYNC Front Porch
VSYNC Pulse Width
VSYNC Back Porch
VSYNC Front Porch
Pin Configuration
Data 0 Pin
Data 1 Pin
Data 2 Pin
Data 3 Pin
Data 4 Pin
Data 5 Pin
Data 6 Pin
Data 7 Pin
Data 8 Pin
Data 9 Pin
Data 10 Pin
Data 11 Pin
Data 12 Pin
Data 13 Pin
Data 14 Pin
Data 15 Pin
Display Command Pin
HSYNC Pin
VSYNC Pin
Data Enable Pin
Clock Pin
SDA Pin (for initialization)
SCL Pin (for initialization)
MIPI DSI Configuration
Bus ID
Channel
Lanes
Clock (MHz)
Use MIPI DMA2D
Power LDO Channel
Power LDO Millivolts
Framebuffer Count
Command Bits
Param Bits
Timing Parameters
HSYNC Pulse Width
HSYNC Back Porch
HSYNC Front Porch
VSYNC Pulse Width
VSYNC Back Porch
VSYNC Front Porch
Touch Configuration
Bus Type
No Touch
SPI
I2C
Include Code
Extra Reset Procedure
Vendor Specific Configuration
Panel Initialization
Horizontal Resolution
Vertical Resolution
Left Overhang
Top Overhang
Right Overhang
Bottom Overhang
Swap X and Y
Mirror X
Mirror Y
Update Rate Limit (milliseconds)
Interrupt Pin
Interrupt On Level
Reset Pin
Reset On Level
SPI Configuration
SPI Host
Clock (MHz)
Command Bits
Param Bits
Pin Configuration
MOSI/Data 0 Pin
MISO/Data 1 Pin
QuadWP/Data 2 Pin
QuadHD/Data 3 Pin
Data 4 Pin
Data 5 Pin
Data 6 Pin
Data 7 Pin
Clock Pin
Chip Select Pin
I2C Configuration
I2C Host
Clock (KHz)
I2C Address
Use Internal Pullups
Command Bits
Param Bits
DC Bit Offset
Control Phase Bytes
Disable Control Phase
Pin Configuration
SDA Pin
SCL Pin
Power Configuration
Bus Type
No Power
SPI
I2C
Include Code
Power Initialization Sequence
Init code
SPI Configuration
SPI Host
Clock (MHz)
Pin Configuration
MOSI/Data 0 Pin
MISO/Data 1 Pin
QuadWP/Data 2 Pin
QuadHD/Data 3 Pin
Data 4 Pin
Data 5 Pin
Data 6 Pin
Data 7 Pin
Clock Pin
Chip Select Pin
I2C Power Management
I2C Host
I2C Address
Clock (KHz)
Use Internal Pullups
Pin Configuration
SDA Pin
SCL Pin
SD Card Configuration
Bus Type
No SD
SPI
MMC
Mount Point
Change Detect Pin
Write Protect Pin
Write Protect On Level
SPI Configuration
SPI Host
Clock (MHz)
Pin Configuration
MOSI/Data 0 Pin
MISO/Data 1 Pin
QuadWP/Data 2 Pin
QuadHD/Data 3 Pin
Data 4 Pin
Data 5 Pin
Data 6 Pin
Data 7 Pin
Clock Pin
Chip Select Pin
Interrupt Pin
MMC Configuration
MMC Host
Clock (MHz)
Pin Configuration
Data 0 Pin
Data 1 Pin
Data 2 Pin
Data 3 Pin
Data 4 Pin
Data 5 Pin
Data 6 Pin
Data 7 Pin
Clock Pin
Command Pin
Use Internal Pullup
Button Configuration
Button Pins
Button On Level
Generated Code
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